Generally, today's devices have systems with multiple power requirements, but which run off of a smaller number of, or even a single, power supplies, such as batteries. This is especially true of system-on-chip (SOC) devices, which contain multiple sections with different power requirements, but contain few connections to different power supplies. This is also true of portable devices that run off a single battery (such as a cellular phone). These devices and SOCs utilize power converters to take a single power source and convert the power to the levels necessary for each section.
FIG. 1 illustrates a typical power converter 101 along with its associated control circuitry 103. The power converter 101 typically comprises a Power P-FET 105 and a Power N-FET 107 in series between a power source 109 and a ground 111. A capacitor 117 runs in parallel with a power load 115, and an inductor 113 is connected between the capacitor 117/power load 115 and the connection between the P-FET 105 and the N-FET 107.
During operation of the power converter 101 the inductor 113 is connected to the power source 109 through the P-FET 105 and N-FET 107, resulting in storage of energy in the combination of inductor 113 and capacitor 117. The control circuitry 103 controls the “on” and “off” states of the P-FET 105 and the N-FET 107 such that the desired output voltage VOut is supplied to the power load 115.
The traditional control circuitry 103 consists of a continuous voltage, discrete time analog circuit comprising a first op amp 119, also called an error amp, a comparator 121, a ramp generator 123, and a pre-driver 125. The positive input to the first op amp 119 is connected to the power converter 101 between the inductor 113 and the capacitor 117/power load 115, while the negative input to the first op amp 119 is connected to a reference voltage VRef. The output of the first op amp 119 is connected to the negative input of the second op amp 121, while the output of the ramp generator 123 is connected to the positive input of the second op amp 121. The output signal from the second op amp 121 is routed to the pre-driver 125, which buffers the signals to the P-FET 105 and the N-FET 107, effectively controlling the power converter 101 in either “on” or “off” mode.
One disadvantage of the analog control circuit 103 is the difficulty in implementing a precise ramp generator 123, and the difficulty in controlling the loop response and dynamic performance of the control circuit 103 and power converter 101 using an analog system because the frequency response of the control loop can only be modified by changing the frequency response of the analog components, requiring a redesign and rebuild. Additionally, some mode of operation, such as pulse frequency modulation, require multiple error amps in order to implement, which increases the complexity of the design and control of the loop response.
Accordingly, what is needed is a control circuit that does not require a ramp generator and that allows easier control of the loop response of the control circuit and reduced complexity.